The present invention pertains to central processor unit control of synchronously operating peripheral units and more particularly to duplex synchronization of asynchronous signals.
When an asynchronous signal is supplied as an input to a synchronous device, the signal is generally synchronized to the internal timing signals of the device. If the device is operated in a duplex mode, that is, there are two identical copies of the device operating together, then this synchronization process can occur at different times in the two copies. This synchronization process will generally occur one clock pulse apart in the two copies due to timing skews between the asynchronous input and due to timing skews between the clock pulses in the two copies. These timing skews may be the result of (1) component tolerances; (2) differing cable lengths; (3) different cable impedances; and (4) temperature differentials. If this synchronization process does occur at different times in the two copies, the result can be different operation cycles in the two copies and non-synchronous operation.
Prior solutions to this problem include synchronizing to a common clock, but due to the critical timing of other dependent units this solution is ineffective.
Accordingly, it is the object of the present invention to provide apparatus for duplex synchronization of asynchronous signals for circuitry which operates other time dependent circuitry.